===== N5991 PCIe Test Automation ===== ======================================================================================================================= 2.20 [released 2020-09-11] ======================================================================================================================= 2.20.0.10 [available 2020-09-11] modification Tested with Z- and V-series oscilloscope FW rev. 6.55.00702 modification Tested with UXR oscilloscope FW rev. 10.25.00702 modification Tested with J-BERT M8070B FW rev. 7.2.40.2. modification Switched to SigTest Phoenix for 32GT/s calibrations. Required SigTest Phoenix version is 5.0.10. new 2.5 and 5GT/s ASIC and CEM Calibrations and Rx Tests for M8040A. new M.2 8GT/s Calibration, Rx- and LEQ-Test. new For M8040 Calibration, Rx- and LEQ-Test can now be done on different M8045A channels new M8047A re-driver support for DUTs with high loss Tx channel. new SigTest Phoenix support for 32G calibrations. new LEQ Tests can be done on other lanes than lane 0 if the DUT supports it. new When using multiple generator channels each channel assigned to a lane can now be calibrated separately for 16 and 32G. Previously it was only possible to use calibration data from lane 0 for those data rates. new If tested instrument version does not match to instrument version of the connected instrument a warning is logged. modification Common jitter tolerance tests for all data rates. modification Using fixed time BER method with 1e10 bits and 5 allowed bit errors for all jitter tolerance tests since this improves the repeatability. modification Using target BER (instead of fixed time) BER method for ASIC Rx compliance test. modification Display range for LEQ Tx Response Time Tests for UXR scopes is now adjusted to internal acquisition range. Before it looked like the range was selected too high and the signal amplitude only filled a very small region of the vertical axis, although for the internal HW acquisition everything was setup correctly. modification Loopback training for 32GT/s Rx Coefficient Matrix Scan and Rx Compliance Tests is now done with all impairments enabled by default. bugfix Capture and Compare Mode for M8040A did not work. bugfix For Gen5 16GT/s Rx Tests Common Clock Architecture 1ns sinusoidal SSC spur was also applied on 100MHz reference clock, but it should only by applied on data out. bugfix The full amount of SJ from Compliance Eye Calibration was applied as first SJ tone plus second tone SJ at 32GT/s Rx Compliance Tests. As first SJ tone only the amount of SJ from Compliance Eye calibration - second SJ tone should be applied. bugfix 32GT/s Jitter Tolerance reported for Min Fail and Max Pass only 1st SJ tone, but reported for Min Spec nominal spec (1st SJ tone) + 2nd SJ tone. Now nominal spec (only 1st SJ tone) is reported. bugfix 32GT/s Jitter Tolerance does not work with non-compliance frequencies. bugfix For target BER measurements which take longer than 10s when BER is close to target BER it could happen that the measurement was aborted before the confidence level was reached. known defect 32GT/s Rx-test with M8062A not tested due to defective M8062A error detector. 32GT/s Calibrations and Rx Setups are tested successfully. ======================================================================================================================= 2.00 [released 2019-10-18] ======================================================================================================================= 2.08 [available 2020-06-15] modification Tested with Z- and V-series oscilloscope FW rev. 6.55.00401 modification Tested with UXR oscilloscope FW rev. 10.20.00503 modification Tested with J-BERT M8070B FW rev. 7.0.640.6. new Added UXR correlation mode: Compliance (Good correlation to older scopes likes Z-Series), Low Noise (takes advantage of lower noise floor of UXR), Custom (customer can choose sampling rate and range to signal ratio for auto-scaling) modification Adjusted UXR sampling rate and range to signal ratio for some calibrations to get better correlation to older scopes. modification Now using SW embedding instead of HW embedding with UXR scopes since this results in better correlation to older scopes. modification For 8, 16 and 32GT/s TxEq calibrations with M8040A system without TTCs and with a 50GHz UXR oscilloscope, 50GHz bandwidth will be used instead of 33GHz. modification Adding Input Range properties for M8046 error detector. modification Adding a workaround for the M8020A CDR sequence control which did not turn off CDR in some cases at interactive loopback training. modification Adding "Use Compliance Impairments" to ASIC 8 GT/s Jitter Tolerance Test. If true impairments according final to eye-calibrations are used. If false the user can change the impairments. modification Changing default value for root-complex / system LTSSM Speed Change Control from DUT to BERT. modification Changing default value for root-complex / system 8, 16 and 32GT/s LTSSM DUT Target Preset from P5 to P7. modification Changing default value for root-complex / system 8, 16 and 32GT/s LTSSM DUT Target Preset from P5 to P7. modification Changing default value for root-complex / system Input Sensitivity: M8020A: 2.5, 5, 8, 16 and 32GT/s from Normal to High. M8040A: N/A. modification Changing default value for root-complex / system Analyzer Equalization: M8020A: 2.5, 5, 8 and 16GT/s from 6 to 9dB and 32GT/s from Medium to High. M8040A: 8, 16, and 32GT/s from 80 to 120. bugfix Impairment settings for PCIe5 ASIC at 8 GT/s Jitter Tolerance Test not applied correctly. bugfix Wrong (interactive) training script was used by default for Rx Setup tests. bugfix Gen3 DUT Tx Target Preset was not set correctly in LTSSM for 16 or 32GT/s Rx tests. bugfix At 32GT/s Compliance Eye Calibration sometimes not the trial with eye-height closest to 15mV was selected. bugfix 32GT/s Channel Calibration with SigTest does not select optimum CTLE result within one CTLE scan for evaluating if another channel is required. bugfix LEQ-Tx test don't work with UXR oscilloscopes. 2.06 [available 2020-03-05] modification Tested with Z- and V-series oscilloscope FW rev. 6.50.01104 modification Tested with UXR oscilloscope FW rev. 10.11.05004 modification Tested with J-BERT M8070B FW rev. 6.7.500.6 modification Updated 16G SigTest version to 4.0.52. modification Adapt API for M8070B 7.0 Interference Generation with AWG. Change is backwards compatible with M8070B 6.7. modification 8, 16 and 32GT/s EQ Coefficient Matrix Scan: Only set TxEQ settings back to training TxEQ settings if error detector has sync loss. modification 16GT/s Compliance Eye Calibration has now properties to limit Vdiff, SJ and DMSI range for eye-height and eye-width search. modification Changed required VFSeasim version to 0.78.0 for 32GT/s new 32GT/s tests can be done on multiple lanes. bugfix For 8GT/s Asic SRIS under spec revision 4 and 5 3000ppm down spread SSC was used. According spec a 25ns sinusoidal SSC spur should be used. bugfix 8 and 16GT/s LEQ Tx tests didn't work on lanes other than lane 0. bugfix AWG channels can be selected in the select lane dialog as DataOut channels. bugfix 32GT/s Jitter Tolerance Test with fixed number of amplitude always just tests 3 amplitudes bugfix For 32GT/s Seasim Calibrations the DMSI loss for end point was always used, even if root complex was selected. bugfix Reference for 32GT/s the latest ctle file gen5_0p7ctlereference_upto200Ghz. Needs to be added to the VFSeasim LEQ_responses folder. bugfix Changed the Seasim config file vf-pcie-gen5.inc to support the gen5_0p7ctlereference_upto200Ghz.pkl LEQ file. bugfix Use the 32GT/s package model without the causality issue. Changed filename to make sure the new transfer function is copied to the scope. bugfix Multilane selection did not have any effect for 32GT/s Calibrations and Tests. bugfix Residual SSC for 16GT/s ASIC Rx test was not applied to M8040A system. bugfix Loading a .vfc/.vfp did not always load all procedures that were stored. (Especially 32GT/s procedures could be missing). bugfix Loading a configuration with enabled lane mapping resulted in errors. The lane mapping is now stored correctly in the .vfp/vfc. files. bugfix User definition for custom ISI emulation settings was overridden with default settings. bugfix ISI emulation state is now also loaded from the caldata. 2.04 [available 2019-12-06] modification If an UXR oscilloscope is used 16G ISI calibration is not done with step response measurement. modification Display a warning in Common Clock architecture when the 100MHz reference clock input contains SSC. Using SSC leads to an undefined test condition because the propagation time differences in the test setup between clock and data can be greater than the spec defines it for a real system. This can result in over stressing the DUT. It is highly recommended to turn SSC off. modification Sometimes it happened that data output went off before loopback training. Now ValiFrame checks the data state before loopback training and tries to re-enable data outputs. bugfix When loading test configuration from .vfp file 8G Tests did not update the calibration dependent impairment values according to the current caldata but instead used the saved values. 2.03 [available 2019-11-22] new Option N5991PB4A and N5991PC4A supports now additional spec version 1.0, 1.1 and 2.0 if an M8020A setup is used. 2.02 [available 2019-11-21] bugfix On freshly installed PCs Test Automation could not start with message "Error in Station Startup". 2.01 [available 2019-11-15] modification Tested with M8070B 6.7.330.4 modification Tested with M8196A SFP 2.1.0.0 modification Tested with M8195A SFP 4.0.0.0 modification Tested with Z- and V-series oscilloscope FW rev. 6.40.01101 modification Tested with UXR oscilloscope FW rev. 10.11.04711 modification Tested with VFSeasim version 0.74.0_2 modification Tested with 32G SigTest version 4.0.39, 16G SigTest version 4.0.51 and 8G SigTest version 3.2.0.3. bugfix M8046A analyzer equalization feature up to 32Gbaud is not recognized by the SW. bugfix At Rx tests with M8040A system the M8046A error detector CDR sometimes does not lock before LB training in static or vendor specific training mode. modification "SKIP BER Check" for LEQ Transmitter tests is now set to true by default for M8040A. modification Offset for the response signal at Link EQ Transmitter Response Tests is slightly shifted up in order the whole response signal fits on the scope display. modification Option to ignore protocol response time for pass/fail at LEQ Tx Response Time Tests (only consider electrical response time). known defect At Rx tests with M8040A system the M8046A error detector CDR sometimes does not lock before LB training in static or vendor specific training mode. Workaround: when asked to power cycle DUT, set expected symbol rate to 7.99999Gbaud/s (8GT/s) or 15.99999Gbaud/s (16GT/s) in M8070B GUI for M8046A CDR settings. known defect Sometimes the starting sampling delay of M8046A error detector doesn't fit to the channel or DUT Tx equalization and M8040A LTSSM doesn't train. Workaround: change sampling delay manually in M8070B GUI until DUT trains into loopback. known defect For long traces on DUT Tx path (mostly server or systems) M8046A error detector cannot equalize the ISI anymore. Workaround: connect an external equalizer (CTLE and DFE) on M8046A ED inputs. 2.00 [available 2019-10-18] modification Tested with M8070B 6.7.330.4 modification Tested with M8196A SFP 2.1.0.0 modification Tested with M8195A SFP 3.6.0.0 modification Tested with Z- and V-series oscilloscope FW rev. 6.40.01101 modification Tested with UXR oscilloscope FW rev. 10.11.04711 modification Tested with VFSeasim version 0.74.0_2 modification Tested with 32G SigTest version 4.0.39, 16G SigTest version 4.0.51 and 8G SigTest version 3.2.0.3. new M8020A setup: added Gen4 tests for Asic (2.5 - 16GT/s), CEM (2.5 - 16GT/s) and U.2 (8GT/s) tests. new M8020A setup: added Gen5 tests for Asic (2.5 - 16GT/s). Note: currently CEM (2.5 - 16GT/s) and U.2 (8GT/s) are also include for Gen5 but since no Gen5 PHY Test specification / Gen5 CEM specification is available the test are done against Gen4 PHY Test Specification / CEM Test Specification . new M8040A setup: added Gen4 tests for Asic (8 and 16GT/s), CEM (8 and 16GT/s) and U.2 (8GT/s). new M8040A setup: added Gen5 tests for Asic (8 and 16GT/s). Note: currently CEM (8 and 16GT/s) and U.2 (8GT/s) is also include for Gen5 but since no Gen5 PHY Test Specification is available the test are done against Gen4 PHY Test Specification. modification Changed 32GT/s procedure base ID form 300000 to 400000 since 32GT/s IDs collided with lower data rate IDs. known defect Sometimes the starting sampling delay of M8046A error detector doesn't fit to the channel or DUT Tx equalization and M8040A LTSSM doesn't train. Workaround: change sampling delay manually in M8070B GUI until DUT trains into loopback. known defect For long traces on DUT Tx path (mostly server or systems) M8046A error detector cannot equalize the ISI anymore. Workaround: connect an external equalizer (CTLE and DFE) on M8046A ED inputs. ======================================================================================================================= 1.00 [released 2019-08-01] ======================================================================================================================= 1.00 [available 2019-08-01] new Initial release for N5991 PCIe Gen5 (32GT/s) modification Tested with M8070B 6.5.550.2 modification Tested with M8196A SFP 2.1.0.0 modification Tested with M8195A SFP 3.6.0.0 modification Tested with Z-Series oscilloscope FW 06.40.01001 modification Tested with VFSeasim 0.74.0_2 modification Tested with Gen5 SigTest version 4.0.41